Junction FET
Depletion Mode만을 사용하며 Source-Drain 영역사이에 Ion주입 혹은 확산공정에 의한 Gate전극을 만들고 Gate에 걸어주는 전압에 의한 Drain전류를 제어하는 FET(Field Effect Transistor)를 일컬음.
[ J-Lead ]
Lead 구성은 Plastic chip carrier package로 보통 구성된다. J-lead는 Package
몸체 아래로 Lead가 구부려 진다. 측면에서 보면 "J"형상을 가진다.
A lead configuration typically used on plastic chip carrier packages which have leads that are bent underneath the package body. A side view of the formed lead resembles the shape of the letter "J."
[ J-STD ]
Joint Industry Standards
[ J-STD-001 ]
Requirements for Soldered Electrical and Electronic Assemblies
[ J-STD-002 ]
Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires
[ J-STD-003 ]
Solderability Tests of Printed Boards
[ J-STD-004 ]
Requirements for Soldering Fluxes
[ J-STD-005 ]
General Requirements and Test Methods for Electronic Grade Solder Paste
[ J-STD-006 ]
General Requirements and Test Methods for Soft Solder Alloys and Fluxed and Non-Fluxed Solid Solders for
[ J-STD-012 ]
Implementation of Flip Chip and Scale Chip Technology
